Modern processors have the ability to expose internal performance measurements, such as L1 cache miss or branch misprediction to the advanced user. This is done by calling OS kernel-supported system calls, which cause dedicated registers, called “performance counters”, to expose different performance measures simultaneously, in resolutions of single cycles. Each phase is characterized by its own different temporal behavior, and it turns out that each phase corresponds to a different loop in the code. In this project we define and tackle 2 problems – phase detection and phase prediction. For the former we formulate a statistical tool – hypothesis testing – which determines when a program phase has changed by sampling one or more specific performance counters and calculating the appropriate statistical estimators. After detection has been done, the latter – phase prediction – is performed. That is done after learning the history of past phases, and using this history to predict future phases. To test our results, we both generate synthetic data and obtain real data using the SPEC2006 benchmark suite. The end result is a satisfying ability for both detection and prediction of the different phases.
Student(s): Gal Dalal
Supervisor(s): Shie Mannor, Uri Weiser